The present invention relates to a serial data transfer apparatus for use in the field of serial data communications wherein serial data is transferred in accordance with predetermined rules, that is, protocol.
An example of a configuration of a serial data reception circuit employed by a conventional serial data transfer apparatus is described with reference to FIG. 1 by way of an example of the case wherein serial data received by the serial data transfer apparatus (the data is hereinafter referred to as "reception serial data") is sent to a central processing unit of a microcomputer.
The serial data reception circuit includes a reception buffer 1 connected to the central processing unit of the microcomputer (not shown in FIG. 1) through a data bus 7, a shift clock generation circuit 10, a shift register 2, a control circuit 3, a pointer 4, an input buffer 5, a multiplexer 6 connected to the central processing unit through an address bus 8, and a reception serial data input terminal 9. It is to be noted that, according to the protocol of reception serial data (R.times.D), as seen in FIG. 2(a), a falling edge of the reception serial data (R.times.D) indicates the starting position of the serial data communication, and first to third units of reception data D.sub.R1 -D.sub.R3, each of which consists of 8 bits, are transferred serially following the falling edge. The period for which the first unit of reception data D.sub.R1 consisting of 8 bits is transferred is called a first reception frame F.sub.R1 ; the period for which the second unit of reception data D.sub.R2 consisting of 8 bits is transferred is called a second reception frame F.sub.R2 ; and the period for which the third unit of reception data D.sub.R3 consisting of 8 bits is transferred is called a third reception frame F.sub.R3.
In the serial data reception circuit, the reception serial data (R.times.D) is inputted from the reception serial data input terminal 9 to the input buffer 5 and then inputted from the input buffer 5 to the shift clock generation circuit 10, the shift register 2 and the control circuit 3. In the shift clock generation circuit 10, a shift clock signal (SCK) synchronized with the reception serial data (R.times.D) is generated from the falling edge of the reception serial data (R.times.D) by using a system clock signal (C1) inputted thereto from the outside. When the falling edge of the reception serial data (R.times.D) is detected, the control circuit 3 executes the initialization of the communication control thereof, and a clear signal (CLR) for initializing the pointer 4 which designates an address of the reception buffer 1 is outputted from the control circuit 3 to the shift clock generation circuit 10 and a clear terminal CLR' of the pointer 4 as shown in FIG. 2(c). In the shift register 2, the reception serial data (R.times.D) is shifted one bit at a time in synchronism with a shift clock signal (SCK) transmitted thereto from the shift clock generation circuit 10 so that the first unit of reception data D.sub.R1 is fetched into the shift register 2. In this instance, the control circuit 3 calculates the shift amount of the shift register 2 by using the shift clock signal (SCK) transmitted thereto from the shift clock generation circuit 10. At the point of time when the calculated shift amount becomes equal to "8," an increment/write control signal (INC/WR) of high level is outputted from the control circuit 3 to a write control signal input terminal WR of the reception buffer 1 and an increment control signal input terminal INC of the pointer 4 as shown in FIG. 2(b). Here, the increment/write control signal (INC/WR) is a signal to write data in the shift register 2 into the reception buffer 1 and increment the address of the reception buffer 1 designated by the pointer 4. As a result, the first unit of reception data D.sub.R1 is written into the address designated by the pointer 4 of the reception buffer 1.
Thereafter, the second unit of reception data D.sub.R2 and the third unit of reception data D.sub.R3 are successively written into the reception buffer 1 in a similar manner as in the case of the first unit of reception data D.sub.R1. After the writing of the third unit of reception data D.sub.R3 into the reception buffer 1 is completed, an interrupt requesting signal (INT) of high level representing that the reception of all of the reception serial data has been completed is generated in the control circuit 3 as shown in FIG. 2(d) and then outputted from the control circuit 3 to the central processing unit. When the interrupt requesting signal (INT) is inputted, the central processing unit reads out the designated address of the reception buffer 1 through the address bus (not shown in FIG. 1). A read-out control signal (R.times.BRD) of high level is outputted from the central processing unit to a read-out control signal input terminal RD of the reception buffer 1 and the multiplexer 6, and an address signal is outputted from the central processing unit to an address signal input terminal AD of the reception buffer 1 through the address bus 8 and the multiplexer 6. Consequently, the first to third units of reception data D.sub.R1 -D.sub.R3 written in the reception buffer 1 are read out from the reception buffer 1 to the central processing unit through the data bus 7.
In recent years, systems which employ a large number of microcomputers have been increasing in number. In such a system, the entire system must operate in a synchronized condition. To this end, communications of data are performed very frequently and closely between the microcomputers. In order to allow a plurality of microcomputers to operate closely and efficiently, time management is required for communications of data generally since communications of real time data increase. It is to be noted that real time data signifies data which varies with respect to time.
A microcomputer requires, depending upon the program being executed, a certain interval of time until reading out processing of data of the reception buffer 1 is performed actually after the interrupt requesting signal (INT) is accepted. When this time difference exists, some correction is necessary when the real time data to be transferred is to be processed. Further, when serial data is communicated in a fixed period, the microcomputer must know at which time the reception serial data stored in the reception buffer 1 was communicated and execute processing of the reception serial data read out from the reception buffer 1 in accordance with the time.
However, the conventional serial data transfer apparatus described above is disadvantageous in that, when the reception serial data is to be received, only the interrupt requesting signal (INT) of high level is generated, and consequently, the time management of the reception serial data is impossible and the control essential to communications of the real time data cannot be performed. Further, when the serial data is to be transmitted, it is necessary to recognize the time for which the transmission has actually been performed and correct a serial data to be transmitted next in accordance with the time. However, since the conventional serial data transfer apparatus cannot perform the control just described, it is disadvantageous also in that the transmission of real time data cannot be performed.